Logic gates

What is a logic gate?

In plain words: a logic gate answers a yes-or-no question about its inputs. An AND gate says “yes” only if every input says “yes”; an OR gate says “yes” if any input does; a NOT gate turns “yes” into “no” and “no” into “yes”. Wire enough of these together and you can build a calculator or a computer.

Truth tables

• A logic variable has two logic states, 1 and 0, which stand for TRUE and FALSE (NEETS Module 13, page 2-2). In a circuit they are two logic levels, HIGH and LOW. In positive logic, the one used on this page, the 1 state is the more positive voltage (page 2-3).
• A truth table lists every possible combination of the inputs with the output for each (page 2-5). With n inputs there are 2ⁿ combinations: 4 rows for two inputs, 8 for three (page 2-8):

• To be sure no row is missing, write the inputs in the order of counting in binary: 00, 01, 10, 11 for two inputs (reasoned).
• A gate’s rule can also be written as a Boolean expression. The plus sign means OR and is not addition; a dot, or two letters side by side, means AND; a bar over a letter or expression means NOT, its complement (NEETS Module 13, pages 2-2, 2-6 and 2-10). So in logic 1 + 1 = 1.

Real HIGH and LOW levels are voltage ranges, not universally 1 V and 0 V. A voltage between the specified input ranges is not a guaranteed logic state. For example, the TI SN7400 datasheet specifies LOW input at or below 0.8 V and HIGH at or above 2.0 V under its operating conditions. These thresholds are family-specific.

OR, AND and NOT gates

• OR gate, Y = A + B: the output is 1 if at least one input is 1, and 0 only when every input is 0 (NEETS Module 13, page 2-10). It works like two switches in parallel lighting a lamp: closing either switch lights it.
• AND gate, Y = A·B: the output is 1 only when all the inputs are 1 at the same time (page 2-6). It works like two switches in series: both must be closed.
• NOT gate (inverter), $Y = \overline{A}$: one input, and the output is its opposite, 0 for 1 and 1 for 0 (page 2-12).

• For 0 and 1, AND gives the same results as ordinary multiplication, while OR differs from addition only in 1 + 1 = 1 (reasoned from the tables).

NAND and NOR gates

• NAND gate, $Y = \overline{A \cdot B}$: an AND gate with a NOT gate at its output. Its output is 0 only when all the inputs are 1, and 1 when any input is 0 (NEETS Module 13, page 2-14).
• NOR gate, $Y = \overline{A + B}$: an OR gate with a NOT gate at its output. Its output is 1 only when all the inputs are 0 (page 2-16).

• De Morgan’s theorem (NEETS Module 13, page 2-31) connects them with OR and AND. Each line can be checked by its truth table; Example 5 checks the second:

• Universal gates: NAND gates alone, or NOR gates alone, can be combined to do the work of every other gate, so they are called universal logic gates (Wikipedia, “Logic gate”). The basic steps:
  • NOT from NAND: join the two inputs, so both are A: the output is $\overline{A \cdot A}$, which is $\overline{A}$ (Wikipedia, “NAND logic”). In the same way a NOR gate with its inputs joined is a NOT gate (reasoned; extras Q5).
  • AND from NAND: a NAND gate followed by a NAND gate used as NOT (Example 3).
  • OR from NAND: make $\overline{A}$ and $\overline{B}$ with two NAND gates used as NOT, and feed them into a third NAND gate. By De Morgan’s theorem its output is A + B:

• With NOR gates the steps mirror these: a NOR gate followed by a NOR gate used as NOT gives OR, and a NOR gate fed with $\overline{A}$ and $\overline{B}$ gives AND, by De Morgan’s theorem (Wikipedia, “NOR logic”):

• In practice, gates come as integrated circuits; the standard 14-pin 7400 chip, for example, holds four independent two-input NAND gates (TI datasheet). The NCERT Laboratory Manual (Physics, Class 12), Project 5, designs an automatic traffic-signal system from logic gates and lists two NOT gates or a single IC 7400, and four NAND gates or a single IC 7400 (page 223): a NAND gate with its inputs joined works as a NOT gate. The project’s self-assessment asks you to design OR, AND and NOT gates from NAND gates (page 226).

Solved examples

Common mistakes to avoid

Quick revision summary

• Logic states 1 and 0 (HIGH and LOW in positive logic); a truth table lists the output for all 2ⁿ combinations of n inputs.
• OR: 1 if any input is 1. AND: 1 only if all inputs are 1. NOT: inverts its one input.
• NAND: AND then NOT, 0 only if all inputs are 1. NOR: OR then NOT, 1 only if all inputs are 0.
• NAND alone, or NOR alone, can make every other gate (universal gates); join the inputs to make a NOT gate.
• De Morgan’s theorem: NOT of an AND is the OR of the NOTs, and NOT of an OR is the AND of the NOTs.

Questions students ask

Are logic gates in the JEE Main and NEET syllabus, and are they in NCERT?

Yes, logic gates are in both syllabuses: Unit 19, Electronic Devices, of the JEE Main syllabus and of the NEET (UG) 2026 syllabus ends with “Logic gates (OR. AND. NOT. NAND and NOR).”, printed the same way in both. They are not in the current NCERT Class 12 Physics Part II, however: its Chapter 14, still the 2025–26 reprint, ends with rectifiers in Section 14.7 and does not mention logic gates or Boolean algebra. The NCERT Laboratory Manual (Physics, Class 12) does use them, in Project 5, which designs an automatic traffic-signal system from logic gates (page 223).

What is the difference between basic gates and universal gates?

Basic gates are OR, AND and NOT, as the NCERT Laboratory Manual (Physics, Class 12) calls them (page 226); beyond the NCERT text, together they can implement any Boolean combinational function, while the universal gates, NAND and NOR, can each build every other gate on its own (Wikipedia, “Functional completeness”). AND and OR alone are never universal: raising an input from 0 to 1 never lowers their output, so no combination of them gives NOT, whereas NAND and NOR carry the inversion inside. Among single two-input Boolean operations, NAND and NOR are the individually universal ones. Feedback and storage introduce sequential-circuit behaviour, which needs more than a truth table of current inputs alone.

How many NAND gates are needed to make NOT, AND, OR, NOR and XOR gates?

Making gates from two-input NAND gates alone takes, beyond the NCERT text, one NAND gate for NOT, two for AND, three for OR, four for NOR and four for XOR (Wikipedia, “NAND logic”). NOR is the three-gate OR followed by a fourth NAND gate used as NOT; XOR feeds A and B into one NAND gate, then that output with A and with B into two more, whose outputs a fourth NAND gate combines. With NOR gates the roles swap: one for NOT, two for OR, three for AND and four for NAND (Wikipedia, “NOR logic”).

How are logic gates made from diodes and transistors?

Logic gates are made, beyond the NCERT text, from diodes or transistors switched by the inputs, and integrated circuits of MOSFETs are now the usual kind (Wikipedia, “Logic gate”). In a diode OR gate each input feeds a diode to one output tied to earth through a resistor, so any HIGH input forward biases its diode and pulls the output HIGH; reversed diodes and a resistor to the supply make an AND gate (Wikipedia, “Diode logic”). In conventional electronic logic, inversion and restoration of usable output levels require active devices, so logic families add transistors: resistor–, diode– and transistor–transistor logic (RTL, DTL, TTL) and CMOS (NEETS Module 13, pages 3-39 to 3-40).

How is De Morgan’s theorem used with logic gates?

De Morgan’s theorem is used with logic gates to swap AND for OR by inverting the inputs and the output, beyond the NCERT text: a NAND gate gives the same output as an OR gate with both inputs inverted, one of the equivalent pairs that the US Navy’s NEETS Module 13 tabulates (pages 2-21 to 2-22). That is how a circuit of AND and OR gates is rebuilt from NAND gates alone: Y = A·B + C·D equals NOT [NOT (A·B)·NOT (C·D)], two NAND gates feeding a third (reasoned). The theorem holds for any number of inputs, as in NOT (A·B·C) = (NOT A) + (NOT B) + (NOT C); the same law for sets is on the complement of a set page.

How many logic gates are there?

Seven familiar gate types are commonly named in digital electronics, beyond the NCERT text: NOT, OR, AND, NOR, NAND, XOR and XNOR (Wikipedia, “Logic gate”). This is not an exhaustive count of possible Boolean functions. The JEE Main and NEET (UG) 2026 syllabuses list five of them, OR, AND, NOT, NAND and NOR; of the other two, a two-input XOR gate gives a HIGH output when one and only one input is HIGH, and a two-input XNOR gate when both inputs are LOW or both are HIGH (US Navy, NEETS Module 13, glossary, second page).

Practice questions

Try each question first, then open the answer to check your working.

1. Q1. How many rows has the truth table of a four-input NAND gate, and in how many of them is the output 0?

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   2⁴ = 16 rows. The output is 0 in only one of them, when all four inputs are 1.

2. Q2. For A = 1 and B = 0, give the outputs of the OR, AND, NAND and NOR gates.

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   OR 1, AND 0, NAND 1, NOR 0.

3. Q3. A three-input gate gives an output of 1 only when all three inputs are 0. Name it, and give its output for A = 0, B = 1, C = 0.

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   A NOR gate (NEETS Module 13, page 2-16). One input is 1, so the output is 0.